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4-mbit (128k x 32) pipelined sync sram cy7c1339g cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05520 rev. *f revised july 5, 2006 features ? registered inputs and outputs for pipelined operation ? 128k 32 common i/o architecture ? 3.3v core power supply (v dd ) ? 2.5v/3.3v i/o power supply (v ddq ) ? fast clock-to-output times ? 2.6 ns (for 250-mhz device) ? provide high-performance 3-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed writes ? asynchronous output enable ? available in lead-free 100-pin tqfp package, lead-free and non-lead-free 119-ball bga package ? ?zz? sleep mode option functional description [1] the cy7c1339g sram integrates 128k x 32 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw [a:d] , and bwe ), and global write ( gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write co ntrols are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin descriptions and truth table for further details). write cycles can be one to four bytes wide as controlled by the byte write control inputs. gw when active low causes all bytes to be written. the cy7c1339g operates from a +3.3v core power supply while all outputs may operate with either a +2.5 or +3.3v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. 1 note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a0, a1, a bw b bw c bw d bw a memory array dqs sleep control zz a [1:0] 2 dq a byte w rite register dq b byte write register dq c byte w rite register dq d byte write register dq a byte write driver dq b byte write driver dq c byte write driver dq d byte write driver logic block diagram
cy7c1339g document #: 38-05520 rev. *f page 2 of 18 pin configurations selection guide 250 mhz 200 mhz 166 mhz 133 mhz unit maximum access time 2.6 2.8 3.5 4.0 ns maximum operating current 325 265 240 225 ma maximum cmos standby current 40 40 40 40 ma a a a a a 1 a 0 nc/72m nc/36m v ss v dd nc/18m nc/9m a a a a a a a nc dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a nc nc dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d nc a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode byte a byte b byte d byte c cy7c1339g 100-pin tqfp pinout
cy7c1339g document #: 38-05520 rev. *f page 3 of 18 pin configurations (continued) pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the 128k address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1, a0 are fed to the two-bit counter. . bw a , bw b bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are wr itten, regardless of the values on bw [a:d] and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device.ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. ce 3 is sampled only when a new external address is loaded. not connected for bga. where referenced, ce 3 is assumed active throughout this document for bga. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as out puts. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. 234 567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m nc dq c dq d dq c dq d aa aa adsp v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc nc nc nc nc nc/36m nc/72m nc v ddq v ddq v ddq aa a a nc/9m a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode nc nc bw b bw c nc v dd nc bw a nc bwe bw d zz 119-ball bga pinout
cy7c1339g document #: 38-05520 rev. *f page 4 of 18 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 2.6 ns (250-mhz device). the cy7c1339g supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with ei ther the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the firs t address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw [a:d] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clo ck rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advan cement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a se lected state, its outputs are always tri-stated during the firs t cycle of the access. after the first cycle of the acce ss, the outputs are controlled by the oe adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically incr ements the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1, a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1, a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. fo r normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dqs i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-ch ip data register that is triggered by the rising edge of clk. as outputs, they de liver the data contained in the memory location specified by the addresses presen ted during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs are placed in a tri-state condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ssq i/o ground ground for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc,nc/9m, nc/18m. nc/72m, nc/144m, nc/288m, nc/576m, nc/1g ? no connects . not internally connected to the die. nc/9m, nc/18m, nc/72m, nc/144m, nc/288m, nc/576m and nc/1g are address expansion pins are not internally connected to the die. pin definitions (continued) name i/o description
cy7c1339g document #: 38-05520 rev. *f page 5 of 18 signal. consecutive single r ead cycles are supported. once the sram is deselected at clo ck rise by the chip select and either adsp or adsc signals, its output will tri-state immedi- ately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw [a:d] ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses re quire two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqs inpu ts is written into the corre- sponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw [a:d] signals. the cy7c1339g provides byte write capability that is described in the write cycl e descriptions table. asserting the byte write enable input (bwe ) with the selected byte write (bw [a:d] ) input, will selectively write to only the desired bytes. bytes not selected dur ing a byte write operation will remain unaltered. a synchron ous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1339g is a common i/o device, the output enable (oe ) must be deserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are aut omatically tri-stated whenever a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [a:d] ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is conducted, only the se lected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1339g is a common i/o device, the output enable (oe ) must be deserted high before presenting data to the dqs inputs. doing so will tri-state the output drivers. as a safety precaution, dqs are aut omatically tri-stated whenever a write cycle is detected, re gardless of the state of oe . burst sequences the cy7c1339g provides a tw o-bit wraparound counter, fed by a1, a0, that implements either an interleaved or linear burst sequence. the interleaved burs t sequence is designed specif- ically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1, a0 second address a1, a0 third address a1, a0 fourth address a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 40 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to snooze current th is parameter is sampled 2t cyc ns t rzzi zz inactive to exit snooze cu rrent this parameter is sampled 0 ns
cy7c1339g document #: 38-05520 rev. *f page 6 of 18 truth table [2, 3, 4, 5, 6, 7] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l-h tri-state deselect cycle, power-down none l l x l l x x x x l-h tri-state deselect cycle, power-down none l x h l l x x x x l-h tri-state deselect cycle, power-down none l l x l h l x x x l-h tri-state deselect cycle, power-down none l x h l h l x x x l-h tri-state snooze mode, power-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes: 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals (bw a , bw b , bw c , bw d ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b , bw c , bw d ), bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. bga package has only 2 chip selects ce 1 and ce 2 . 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw [a: d] . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselect ed, and all data bits behave as output when oe is active (low).
cy7c1339g document #: 38-05520 rev. *f page 7 of 18 partial truth table for read/write [2, 8] function gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? dq a hlhhhl write byte b ? dq b hlhhlh write bytes b, a h l h h l l write byte c? dq c hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d? dq d hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx note: 8.table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active.
cy7c1339g document #: 38-05520 rev. *f page 8 of 18 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +4.6v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc voltage applied to outputs in tri-state ............................................ ?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ?5%/+10% 2.5v ?5% to v dd industrial ?40c to +85c automotive ?40c to +125c electrical characteristics over the operating range [9, 10] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage for 3.3v i/o, i oh = ?4.0 ma 2.4 v for 2.5v i/o, i oh = ?1.0 ma 2.0 v v ol output low voltage for 3.3v i/o, i ol = 8.0 ma 0.4 v for 2.5v i/o, i ol = 1.0 ma 0.4 v v ih input high voltage [9] for 3.3v i/o 2.0 v dd + 0.3v v for 2.5v i/o 1.7 v dd + 0.3v v v il input low voltage [9] for 3.3v i/o ?0.3 0.8 v for 2.5v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?30 a input = v dd 5 a input current of zz input = v ss ?5 a input = v dd 30 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz 325 ma 5-ns cycle, 200 mhz 265 ma 6-ns cycle, 166 mhz 240 ma 7.5-ns cycle, 133 mhz 225 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max = 1/t cyc 4-ns cycle, 250 mhz 120 ma 5-ns cycle, 200 mhz 110 ma 6-ns cycle, 166 mhz 100 ma industrial/ commercial 7.5-ns cycle, 133 mhz 90 ma automotive 7.5-ns cycle, 133 mhz 115 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 40 ma notes: 9. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 10. tpower-up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1339g document #: 38-05520 rev. *f page 9 of 18 i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 4-ns cycle, 250 mhz 105 ma 5-ns cycle, 200 mhz 95 ma 6-ns cycle, 166 mhz 85 ma 7.5-ns cycle, 133 mhz 75 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il , f = 0 all speeds 45 ma capacitance [11] parameter description test conditions tqfp package bga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v. v ddq = 3.3v 55pf c clk clock input capacitance 5 5 pf c i/o input/output capacitance 5 7 pf thermal resistance [11] parameter description test conditions tqfp package bga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 30.32 34.1 c/w jc thermal resistance (junction to case) 6.85 14.0 c/w ac test loads and waveforms note: 11. tested initially and after any design or proc ess change that may affect these parameters. electrical characteristics over the operating range [9, 10] (continued) parameter description test conditions min. max. unit output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 3.3v i/o test load 2.5v i/o test load output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1 ns 1 ns (c) 2.5v i/o test load
cy7c1339g document #: 38-05520 rev. *f page 10 of 18 switching characteristics over the operating range [12, 13, 14, 15, 16, 17] parameter description ?250 ?200 ?166 ?133 unit min. max. min. max. min. max. min. max. t power v dd (typical) to the first access [12] 11 11ms clock t cyc clock cycle time 4.0 5.0 6.0 7.5 ns t ch clock high 1.7 2.0 2.5 3.0 ns t cl clock low 1.7 2.0 2.5 3.0 ns output times t co data output valid after clk rise 2.6 2.8 3.5 4.0 ns t doh data output hold after clk rise 1.0 1.0 1.5 1.5 ns t clz clock to low-z [13, 14, 15] 00 00ns t chz clock to high-z [13, 14, 15] 2.6 2.8 3.5 4.0 ns t oev oe low to output valid 2.6 2.8 3.5 4.0 ns t oelz oe low to output low-z [13, 14, 15] 00 00ns t oehz oe high to output high-z [13, 14, 15] 2.6 2.8 3.5 4.0 ns set-up times t as address set-up before clk rise 1.2 1.2 1.5 1.5 ns t ads adsc , adsp set-up before clk rise 1.2 1.2 1.5 1.5 ns t advs adv set-up before clk rise 1.2 1.2 1.5 1.5 ns t wes gw , bwe , bw x set-up before clk rise 1.2 1.2 1.5 1.5 ns t ds data input set-up before clk rise 1.2 1.2 1.5 1.5 ns t ces chip enable set-up before clk rise 1.2 1.2 1.5 1.5 ns hold times t ah address hold after clk rise 0.3 0.5 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.3 0.5 0.5 0.5 ns t advh adv hold after clk rise 0.3 0.5 0.5 0.5 ns t weh gw , bwe , bw x hold after clk rise 0.3 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.3 0.5 0.5 0.5 ns t ceh chip enable hold after clk rise 0.3 0.5 0.5 0.5 ns notes: 12. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 13. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 14. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect pa rameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 15. this parameter is sampled and not 100% tested. 16. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 17. test conditions shown in (a) of ac test loads unless otherwise noted.
cy7c1339g document #: 38-05520 rev. *f page 11 of 18 switching waveforms read cycle timing [18] note: 18. on this diagram, when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bw[a:d] d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address don?t care undefined
cy7c1339g document #: 38-05520 rev. *f page 12 of 18 write cycle timing [18, 19] note: 19. full width write can be initiated by either gw low; or by gw high, bwe low and bw [a:d] low. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw[a :d] d ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined
cy7c1339g document #: 38-05520 rev. *f page 13 of 18 read/write cycle timing [18, 20, 21] notes: 20. the data bus (q) remains in high-z following a writ e cycle, unless a new read access is initiated by adsp or adsc . 21. gw is high. switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw[a:d] d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3
cy7c1339g document #: 38-05520 rev. *f page 14 of 18 zz mode timing [22, 23] notes: 22. device must be deselected when entering zz mode. see cycle descr iptions table for all possible signal conditions to deselect the device. 23. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only
cy7c1339g document #: 38-05520 rev. *f page 15 of 18 ordering information not all of the speed, package and temperature ranges are a vailable. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 133 cy7c1339g-133axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1339g-133bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-133bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free cy7c1339g-133axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1339g-133bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-133bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free cy7c1339g-133axe 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free automotive 166 cy7c1339g-166axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial CY7C1339G-166BGC 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-166bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free cy7c1339g-166axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1339g-166bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-166bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free 200 cy7c1339g-200axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1339g-200bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-200bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free cy7c1339g-200axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1339g-200bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-200bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free 250 cy7c1339g-250axc 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free commercial cy7c1339g-250bgc 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-250bgxc 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free cy7c1339g-250axi 51-85050 100-pin thin quad flat pack (14 x 20 x 1.4 mm) lead-free industrial cy7c1339g-250bgi 51-85115 119-ball ball grid array (14 x 22 x 2.4 mm) cy7c1339g-250bgxi 119-ball ball grid array (14 x 22 x 2.4 mm) lead-free
cy7c1339g document #: 38-05520 rev. *f page 16 of 18 package diagrams note: 1. jedec std ref ms-026 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.0098 in (0.25 mm) per side 3. dimensions in millimeters body length dimensions are max plastic body size including mold mismatch 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r 0.08 min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin tqfp (14 x 20 x 1.4 mm) (51-85050) 51-85050-*b
cy7c1339g document #: 38-05520 rev. *f page 17 of 18 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagrams (continued) 1.27 20.32 2 16 5 4 37 l e a b d c h g f k j u p n m t r 12.00 19.50 30 typ. 2.40 max. a1 corner 0.70 ref. u t r p n m l k j h g f e d c a b 21 43 65 7 ?1.00(3x) ref. 7.62 22.000.20 14.000.20 1.27 0.600.10 c 0.15 c b a 0.15(4x) ?0.05 m c ?0.750.15(119x) ?0.25mcab seating plane 0.900.05 3.81 10.16 0.25 c 0.56 51-85115-*b 119-ball bga (14 x 22 x 2.4 mm) (51-85115) all products and company names mentioned in this docu ment may be the trademarks of their respective holders.
cy7c1339g document #: 38-05520 rev. *f page 18 of 18 document history page document title: cy7c1339g 4-mbit (128k x 32) pipelined sync sram document number: 38-05520 rev. ecn no. issue date orig. of change description of change ** 224368 see ecn rkf new data sheet *a 288909 see ecn vbl in ordering info section, changed tqfp to pb-free tqfp added pb-free bg package *b 332895 see ecn syt modified address expansion balls in the pinouts for 100 tqfp and 119 bga package as per jedec standards and updated the pin definitions accordingly modified v ol, v oh test conditions replaced tbds for ja and jc to their respective values on the thermal resis- tance table updated the ordering information by shading and unshading mpns as per availability *c 351194 see ecn pci updated ordering information table *d 366728 see ecn pci added v dd /v ddq test conditions in dc table modified test condition in note# 10 from v ih < v dd to v ih < v dd *e 420883 see ecn rxu converted from preliminary to final changed address of cypress semiconductor corporation on page# 1 from ?3901 north first street? to ?198 champion court? modified ?input load? to ?input leakage current except zz and mode? in the electrical characteristics table replaced package name column with package diagram in the ordering infor- mation table replaced package diagram of 51-85050 from *a to *b added automotive range in operating range table updated the ordering information *f 480368 see ecn vkn added the maximum rating for supply voltage on v ddq relative to gnd. updated the ordering information table.

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